A LOW POWER PIPELINE ADC WITH BACKGROUND CALIBRATION & DIGITAL CORRECTION

Abstract

This paper relates to low power pipeline analog to digital convertor with background calibration and digital correction. The pipeline ADC accomplishes this by a major reduction in the amount of circuitry required in the conversion process. Digital error correction logic and Flash ADC are integrated to form 10-bit pipelined ADC. Op-amp sharing technique have been used to minimize the power consumption in the pipelined ADCs. The power can also be saved by using charge distribution type dynamic comparator which is suitable for pipelined ADC. In the proposed ADC background calibration circuit comprises of a flash type ADC to summon up the data that is the difference in the MDAC requiring the digital error correction to provide a controlled yet comparable output which consumes 182.28 μW per flash ADC.